FPGA 静态显示数码管

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module seg_sel_led(
   input sys_clk,
	input sys_rst_n,
	output reg [5:0] sel,
	output reg [7:0] seg_led
);


parameter MAX_NUM=25'd2500_0000;
reg [24:0] cnt;
reg [3:0]num;
reg flag;
//0.5 s 的延时
always@(posedge sys_clk or negedge sys_rst_n)begin 
   if(!sys_rst_n)
        cnt<=25'd2500_0000;
	else if(cnt>25'd0) 
	     cnt<=cnt-1'd1;
	else   
        cnt<=25'd0;  		  
	 
end 


always@(posedge sys_clk or negedge sys_rst_n)begin 
      if(!sys_rst_n)
		     flag<=1'b0;
		else if(cnt==1'b1)
			  flag<=1'b1;  
	   else 
		     flag<=1'b0;
end 

always@(posedge sys_clk or negedge sys_rst_n)begin 
      if(!sys_rst_n)
		   num<=4'b0000;
	   else if(flag==1)begin 
		   if(num<10) 
			    num<=num+4'b1;
			else 
			     num<=4'b0000;
		end 
		else 
		     num<=num;
end 

always@(posedge sys_clk or  negedge sys_rst_n)begin
    if(!sys_rst_n)begin 
	     sel[5:0]<=6'b111_111;
		  seg_led[7:0]<=8'b0000_0000;
	 end 
	 else if(flag==1)begin 
	     sel[5:0]<=6'b000_000;
	     case(num)
		       4'b0000:seg_led[7:0]<=8'b1100_0000;//0
				 4'b0001:seg_led[7:0]<=8'b1111_1001;//1
				 4'b0010:seg_led[7:0]<=8'b1010_0100;//2
				 4'b0011:seg_led[7:0]<=8'b1011_0000;//3
				 
				 4'b0100:seg_led[7:0]<=8'b1001_1001;//4
				 4'b0101:seg_led[7:0]<=8'b1001_0010;//5
				 4'b0110:seg_led[7:0]<=8'b1000_0100;//6
				 
				 4'b0111:seg_led[7:0]<=8'b1111_1000;//7
				 4'b1000:seg_led[7:0]<=8'b1000_0000;//8
				 4'b0001:seg_led[7:0]<=8'b1001_1000;//9
				 
				 default:;
		  endcase 
	 end 
end 




endmodule