基于FPGA和DDS技术的波形产生（仿真部分）

时间 2021-06-10 标签 dom blog it 变量 module 随机数 sed 软件 select model

本次仿真主要对三个主要的模块进行仿真，分别是key_control模块，DDS波形产生模块以及顶层模块。dom

首先来看第一个部分key_contrtol模块的仿真。blog

`timescale 1ns/1nsit

module tb_key_cntrol ();变量

//参数的设定module

parameter CNT_1MS = 20'd19 ,随机数

CNT_11MS = 21'd69 ,sed

CNT_41MS = 22'd149 ,软件

CNT_51MS = 22'd199 ,select

CNT_60MS = 22'd249 ;model

//wire型变量的定义

wire [3:0] wave_select ;

//reg型变量的定义

reg sys_clk;

reg sys_rst_n;

reg [21:0] tb_cnt;

reg key_in;

reg [1:0] cnt_key;

reg [3:0] key;

defparam key_control_inst.CNT_MAX = 24;

//用initial对reg型变量进行赋值

initial
begin
sys_rst_n = 1'b0;
sys_clk = 1'b0;
key = 4'b0000;
#200;
sys_rst_n = 1'b1;
end

always #10 sys_clk = ~sys_clk;

//tb_cnt:按键过程计数器，经过该计数器的计数时间来模拟按键的抖动过程
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
tb_cnt <= 22'b0;
else if(tb_cnt == CNT_60MS)
tb_cnt <= 22'b0;
else
tb_cnt <= tb_cnt + 1'b1;

//key_in:产生输入随机数，模拟按键的输入状况
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
key_in <= 1'b1;
else if((tb_cnt >= CNT_1MS && tb_cnt <= CNT_11MS)
|| (tb_cnt >= CNT_41MS && tb_cnt <= CNT_51MS))
key_in <= {$random} % 2;
else if(tb_cnt >= CNT_11MS && tb_cnt <= CNT_41MS)
key_in <= 1'b0;
else
key_in <= 1'b1;

always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
cnt_key <= 2'd0;
else if(tb_cnt == CNT_60MS)
cnt_key <= cnt_key + 1'b1;
else
cnt_key <= cnt_key;

always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
key <= 4'b1111;
else
case(cnt_key)
0: key <= {3'b111,key_in};
1: key <= {2'b11,key_in,1'b1};
2: key <= {1'b1,key_in,2'b11};
3: key <= {key_in,3'b111};
default:key <= 4'b1111;
endcase

//key_control模块的实例化

key_control key_control_inst
(
.sys_clk (sys_clk ), //系统时钟,50MHz
.sys_rst_n (sys_rst_n ), //复位信号,低电平有效
.key (key ), //输入4位按键

.wave_select (wave_select) //输出波形选择
);

endmodule

接着是第二部分DDS波形产生模块的仿真

`timescale 1ns/1ns

module tb_dds();

wire [7:0] data_out ;

reg sys_clk ;
reg sys_rst_n ;
reg [3:0] wave_select ;

initial
begin
sys_clk = 1'b0;
sys_rst_n <= 1'b0;

wave_select <= 4'b0000;
#200;
sys_rst_n <= 1'b1;
#10000
wave_select <= 4'b0001;
#8000000;
wave_select <= 4'b0010;
#8000000;
wave_select <= 4'b0100;
#8000000;
wave_select <= 4'b1000;
#8000000;
wave_select <= 4'b0000;
#8000000;
end

always #10 sys_clk = ~sys_clk;

dds dds_inst
(
.sys_clk (sys_clk ), //系统时钟,50MHz
.sys_rst_n (sys_rst_n ), //复位信号,低电平有效
.wave_select (wave_select), //输出波形选择

.data_out (data_out ) //波形输出
);

endmodule

最后是顶层模块的仿真

`timescale 1ns/1ns

module tb_top_dds();

parameter CNT_1MS = 20'd19000 ,
CNT_11MS = 21'd69000 ,
CNT_41MS = 22'd149000 ,
CNT_51MS = 22'd199000 ,
CNT_60MS = 22'd249000 ;

wire dac_clk ;
wire [7:0] dac_data ;

reg sys_clk ;
reg sys_rst_n ;
reg [21:0] tb_cnt ;
reg key_in ;
reg [1:0] cnt_key ;
reg [3:0] key ;

defparam top_dds_inst.key_control_inst.CNT_MAX = 24;

initial
begin
sys_clk = 1'b0;
sys_rst_n <= 1'b0;
key <= 4'b0000;
#200;
sys_rst_n <= 1'b1;
end

always #10 sys_clk = ~sys_clk;

always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
cnt_key <= 2'd0;
else if(tb_cnt == CNT_60MS)
cnt_key <= cnt_key + 1'b1;
else
cnt_key <= cnt_key;

top_dds top_dds_inst
(
.sys_clk (sys_clk ),
.sys_rst_n (sys_rst_n ),
.key (key ),

.dac_clk (dac_clk ),
.dac_data (dac_data )
);

endmodule

将编写好的仿真文件放入modelsim仿真软件里面。能够获得仿真的波形和咱们时序图画出来的波形是一致的。