module seg_led_static_top( input sys_clk, input sys_rst_n, output [5:0] seg_wei, output [7:0] seg_duan ); wire time_flag; //wire clk; time_count u_time_count( .sys_clk (sys_clk), .sys_rst_n (sys_rst_n), .time_flag (time_flag) ); seg_led_static u_seg_led_static( .sys_clk (sys_clk), .sys_rst_n (sys_rst_n), .time_flag (time_flag), .seg_wei (seg_wei), .seg_duan (seg_duan) ); endmodule
module time_count( input sys_clk, input sys_rst_n, output reg time_flag ); reg [24:0] time_num; always @(posedge sys_clk or negedge sys_rst_n)begin if(!sys_rst_n) begin time_num<=25'd0; time_flag<=1'b0; end else begin if(time_num<25'd25_000_000)begin time_num<=time_num+1'b1; time_flag<=1'b0; end else begin time_num<=25'd1; time_flag<=1'b1; end end end endmodule
module seg_led_static( input sys_clk, input sys_rst_n, input time_flag, output reg [5:0] seg_wei, output reg [7:0] seg_duan ); reg [3:0] seg_fsm; always @(posedge sys_clk or negedge sys_rst_n)begin if(!sys_rst_n) seg_fsm<=4'd0; else if(time_flag) begin seg_fsm<=seg_fsm+1'b1; end else seg_fsm<=seg_fsm; end always @(posedge sys_clk or negedge sys_rst_n)begin if(!sys_rst_n) begin seg_wei <=6'b000000; //低电平点亮数码管 seg_duan <=8'b00000000; end else case(seg_fsm) //共阳数码管 /* 4'b0000: seg_duan <=8'b1100_0000; //0 4'b0001: seg_duan <=8'b1111_1001; //1 4'b0010: seg_duan <=8'b0100_1111; 4'b0011: seg_duan <=8'b0000_0000; 4'b0100: seg_duan <=8'b0000_0000; 4'b0101: seg_duan <=8'b0000_0000; 4'b0110: seg_duan <=8'b0000_0000; 4'b0111: seg_duan <=8'b0000_0000; 4'b1000: seg_duan <=8'b0000_0000; 4'b1001: seg_duan <=8'b0000_0000; 4'b1010: seg_duan <=8'b0000_0000; 4'b1011: seg_duan <=8'b0000_0000; 4'b1100: seg_duan <=8'b0000_0000; 4'b1101: seg_duan <=8'b0000_0000; 4'b1110: seg_duan <=8'b0000_0000; 4'b1111: seg_duan <=8'b0000)0000; */ 4'h0 : seg_duan <= 8'b1100_0000; 4'h1 : seg_duan <= 8'b1111_1001; 4'h2 : seg_duan <= 8'b1010_0100; 4'h3 : seg_duan <= 8'b1011_0000; 4'h4 : seg_duan <= 8'b1001_1001; 4'h5 : seg_duan <= 8'b1001_0010; 4'h6 : seg_duan <= 8'b1000_0010; 4'h7 : seg_duan <= 8'b1111_1000; 4'h8 : seg_duan <= 8'b1000_0000; 4'h9 : seg_duan <= 8'b1001_0000; 4'ha : seg_duan <= 8'b1000_1000; 4'hb : seg_duan <= 8'b1000_0011; 4'hc : seg_duan <= 8'b1100_0110; 4'hd : seg_duan <= 8'b1010_0001; 4'he : seg_duan <= 8'b1000_0110; 4'hf : seg_duan <= 8'b1000_1110; default : seg_duan <= 8'b1100_0000; endcase end endmodule
仿真结果以下图:3d
最终实现实验任务!调试
(PS:调试中 顶层时钟不要链接同一个模块的两个端口 sys_clk 形成实验问题)code