module DDS(clk,rst,freq,pha,key,data);
input wire clk; //时钟
input wire rst; //复位信号（低电平有效）
input wire [6 : 0] freq; //频率控制信号
input wire [6 : 0] pha; //相移变量信号
input wire key; //使能开关信号(高电平有效)
output wire [7 : 0] data; //ROM查找表数据
reg [6 : 0] addr;
reg [6 : 0] phase;
reg [6 : 0] frequency;
always @(posedge clk)
begin
if(key == 1)
begin
phase <= pha; //将相移变量值赋给寄存器phase
frequency <= freq; //将频率控制变量值赋给frequency
end
end
always @(posedge clk or negedge rst)
begin
if(!rst)
begin
addr <= 0; //复位
end
else
begin
if(key == 1)
addr <= phase; //将寄存器phase存储的相值赋给addr
else
addr <= addr + frequency; //ROM地址产生
end
end
rom1 rom_1( .address(addr), .clock(clk), .q(data) ); //实例化调用rom1波形查找表endmodule